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Description of the MPU board
In this board there is the MICROPROCESSOR set which is composed of:

1 CPU (6) COSMAC CDP1802.
2 RAM MEMORY (7A) & (7B) 5101.
4 ROM MEMORY (8), (9), (10) & (ll).
2 MEMORY ADDRESS DECODER (3) & (5) 1859.
1 INPUT/OUTPUT DECODER (l) 1853.
1 DUAL D-type Flip-Flop (2) 4013.
1 TIMER COUNTER (4) 4020.

The CPU board controls the operation of the whole machine, following the programme of the ROM memories. It receives and sends the signals coming or with destination to the several elements of the machine through the IOS board, to which it is connected by the connections MRD, 101, 102, 103, 104, 105, 106, 107, TPB, BUS0-BUS7 & CKD.
The DECODERS (3) & (5), generate the addresses A8, A9 & A10 which are not directly obtained from the CPU as the A0-A7, and by means of the outputs CE0, CE1, CE2 & CE3, only connect one of the RAM devices (7) or ROM (8-ll) to the data bus BUS0-BUS7.
The decoder (3) when reciving the TPA pulse, holds the value of MA2 and of MA5. Thus making:

When MA5 is high makes -CS of the RAM (7) selecting low. When MA5 is low makes -CS of the RAM (7) high disconnecting them.

When -MRD is high makes its output CE0 high therefore the decoder (5) will disconnect the ROM.

When MA2 is high makes A10 high. When MA2 is low makes A10 low.

The decoder (5) when receiving TPA holds the value of MA0, MA1 and MA2, MA3 if memories of 1Kx8 are used. It also holds the value of MA3, MA4 if the memories of 2Kx8 are used. Thus making:

1: If MA0, MA1 are high makes A8, A9 high respectively and on the contrary.

2: If the input -EN coming from the circuit (3) is high, all the CE0, CE1, CE2, CE3 are high and the ROM (8-ll) are disconnected.

3: If the input -EN is low, according to the value hold of MA2, MA3 or MA3, MA4, selects one of the ROM making one of the CE^ to CE3 low and the rest high.

The RAM MEMORIES (7A & 7B) are continuously powered, even when the machine is disconnected from the line, by means of a buffer battery which recharges it-self when the machine is connected to the line. This is in order to keep the information stored, which, in another way would be lost. This information co-rresponds to the book-keeping functions, tones, etc. as well as the accumula-tors for coins, games, prizes, etc. These memories are internally disconnec�ted when its input CS (pin 17) is low. It occurs when the a.c. line is discon-nected. In that way the information kept is preserved.
The CPU board (6) controls these memories TAM by means of the addresses MA0 -MA6 which indicate to which word it is addressed and for the signals -MRD, -MWR, -CS.
When the CPU board needs to read or write in the RAM, makes its -CS low through de decoder (3). When it has to read -MRD will be low and -MWR will be high. When it has to write -MRD will be high and -MWR will be low.
As every memory is organized in 256 words of 4 bits, two of them have been placed with all connections in paralel, except the one for the data bus. In the memory (7A) BUS0-BUS3 have been connected and BUS 4-BUS7 in the memory (7B).
The DECODER I/O (l) generates the signals 101 to 107 from N0, Ml, N2, TPA, TPB, which are used to control the IOS board.
The value of N0, Ml, N2- is held from the moment it receives the pulse from TPA until it receives the one from TPB. With these three signals N0, Nl, N2 decoded, eight possible cases are obtained, which correspond to make low all signals I01 to I07 orelse to make high one of them, precisely the one corres-ponding to the input or output device located in the IOS board to which the CPU board wants to connect in order to receive or supply information.
The FLIP-PLOP (2), located on the left hand side of the scheme of the board, generates the clock signal used to transmit syncronously the information that controls the display boards through a shift register located in the IOS board.
The FLIP-FLOP (2), located on the right hand side of the scheme of the board, memorizes the interrupt request generated in the PSU power supply board, at the beginning of each half cycle of the a.c. line. The request is entered in the CPU by its INT input. Once processed, the CPU send a pulse by I07 which resets such memorization (both flip-flop are in the same integrated circuit (2).
The TIMER COUNTER (4), generates a pulse every 2,77 miliseconds which is carried to the INT input of the CPU through the flip-flop located on the right producing an interrupt so that the CPU refresh the information loaded in the multiplexed display.
The -RST signal coming from the PSU power supply is low when the machine is disconnected from the line and also a few tenth of a second after connecting it. In this situation, it disconnects the RAM to preserve their contents and makes the CPU start the reading of the ROM programme by the start of it.
The signal SYNC generated in the PSU board is high during a line half cycle and low during the following and so scoessively. It is connected to the CPU by -EP3 and it is used by that in order to know whether to activate the little lamps connected to the 10 Volts A orelse to the 10 Volts B.

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Description of the MPU board In this board there is the MICROPROCESSOR set which is composed of: 1 CPU (6) COSMAC CDP1802. 2 RAM MEMORY (7A) & (7B) 5101. 4 ROM MEMORY (8), (9), (10) & (ll). 2 MEMORY ADDRESS DECODER (3) & (5) 1859. 1 INPUT/OUTPUT DECODER (l) 1853. 1 DUAL D-type Flip-Flop (2) 4013. 1 TIMER COUNTER (4) 4020. The CPU board controls the operation of the whole machine, following the programme of the ROM memories. It receives and sends the signals coming or with destination to the several elements of the machine through the IOS board, to which it is connected by the connections MRD, 101, 102, 103, 104, 105, 106, 107, TPB, BUS0-BUS7 & CKD. The DECODERS (3) & (5), generate the addresses A8, A9 & A10 which are not directly obtained from the CPU as the A0-A7, and by means of the outputs CE0, CE1, CE2 & CE3, only connect one of the RAM devices (7) or ROM (8-ll) to the data bus BUS0-BUS7. The decoder (3) when reciving the TPA pulse, holds the value of MA2 and of MA5. Thus making: When MA5 is high makes -CS of the RAM (7) selecting low. When MA5 is low makes -CS of the RAM (7) high disconnecting them. When -MRD is high makes its output CE0 high therefore the decoder (5) will disconnect the ROM. When MA2 is high makes A10 high. When MA2 is low makes A10 low. The decoder (5) when receiving TPA holds the value of MA0, MA1 and MA2, MA3 if memories of 1Kx8 are used. It also holds the value of MA3, MA4 if the memories of 2Kx8 are used. Thus making: 1: If MA0, MA1 are high makes A8, A9 high respectively and on the contrary. 2: If the input -EN coming from the circuit (3) is high, all the CE0, CE1, CE2, CE3 are high and the ROM (8-ll) are disconnected. 3: If the input -EN is low, according to the value hold of MA2, MA3 or MA3, MA4, selects one of the ROM making one of the CE^ to CE3 low and the rest high. The RAM MEMORIES (7A & 7B) are continuously powered, even when the machine is disconnected from the line, by means of a buffer battery which recharges it-self when the machine is connected to the line. This is in order to keep the information stored, which, in another way would be lost. This information co-rresponds to the book-keeping functions, tones, etc. as well as the accumula-tors for coins, games, prizes, etc. These memories are internally disconnec�ted when its input CS (pin 17) is low. It occurs when the a.c. line is discon-nected. In that way the information kept is preserved. The CPU board (6) controls these memories TAM by means of the addresses MA0 -MA6 which indicate to which word it is addressed and for the signals -MRD, -MWR, -CS. When the CPU board needs to read or write in the RAM, makes its -CS low through de decoder (3). When it has to read -MRD will be low and -MWR will be high. When it has to write -MRD will be high and -MWR will be low. As every memory is organized in 256 words of 4 bits, two of them have been placed with all connections in paralel, except the one for the data bus. In the memory (7A) BUS0-BUS3 have been connected and BUS 4-BUS7 in the memory (7B). The DECODER I/O (l) generates the signals 101 to 107 from N0, Ml, N2, TPA, TPB, which are used to control the IOS board. The value of N0, Ml, N2- is held from the moment it receives the pulse from TPA until it receives the one from TPB. With these three signals N0, Nl, N2 decoded, eight possible cases are obtained, which correspond to make low all signals I01 to I07 orelse to make high one of them, precisely the one corres-ponding to the input or output device located in the IOS board to which the CPU board wants to connect in order to receive or supply information. The FLIP-PLOP (2), located on the left hand side of the scheme of the board, generates the clock signal used to transmit syncronously the information that controls the display boards through a shift register located in the IOS board. The FLIP-FLOP (2), located on the right hand side of the scheme of the board, memorizes the interrupt request generated in the PSU power supply board, at the beginning of each half cycle of the a.c. line. The request is entered in the CPU by its INT input. Once processed, the CPU send a pulse by I07 which resets such memorization (both flip-flop are in the same integrated circuit (2). The TIMER COUNTER (4), generates a pulse every 2,77 miliseconds which is carried to the INT input of the CPU through the flip-flop located on the right producing an interrupt so that the CPU refresh the information loaded in the multiplexed display. The -RST signal coming from the PSU power supply is low when the machine is disconnected from the line and also a few tenth of a second after connecting it. In this situation, it disconnects the RAM to preserve their contents and makes the CPU start the reading of the ROM programme by the start of it. The signal SYNC generated in the PSU board is high during a line half cycle and low during the following and so scoessively. It is connected to the CPU by -EP3 and it is used by that in order to know whether to activate the little lamps connected to the 10 Volts A orelse to the 10 Volts B. Playmatic repair main page Main
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